Screaming Very Low Power Microprocessor

I have a new article up at ECN Magazine about a microprocessor that can do 90 billion instructions per second for a power cost of about 1 watt. Pretty good huh? It gets better. The chip has 144 processors in the package and when they are all idle the chip uses only 14 microwatts.

GreenArrays (the company that makes the chip) has partnered with another company to make the processor available to hobbyists.

Cross Posted at Power and Control


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13 responses to “Screaming Very Low Power Microprocessor”

  1. Eric Avatar

    Hey nice article! Congratulations!

    It won’t be long before they get so small and powerful that they’ll be running on their own on a tiny amount of solar power, and they’ll be in charge…

  2. Simon Avatar
    Simon

    Thank you!

    You are not too far wrong. The chip is manufactured with a process that is about 15 years old – 180 nm. Currently the top end process is about 25 nm.

    All they need to do to make the chip faster and smaller is go to a more advanced process.

  3. rhhardin Avatar

    Multiple processors is cheating, since it’s rare that you can use them efficiently, in addition to their screwing up cache hits.

  4. Simon Avatar
    Simon

    There is no cache. And since when is having a math coprocessor cheating?

    The design is more DSP like than microprocessor like. i.e. very nice for a cell phone or high end process controller.

    Like so much that Chuck Moore does very few understand his genius. As kind of a sub genius my job is to make what he has done intelligible to those who don’t get it off the bat.

  5. rhhardin Avatar

    To use a processor array, you need a problem that breaks down into independent parts, namely parts where the computation of one part does not depend on the completion of any other part.

    There certainly are such problems, but they’re pretty specialized.

    Lacking that, the thing runs at the speed of a single processor.

    If it’s a single processor, you get a nice speedup from a cache.

  6. Simon Avatar
    Simon

    With so many interfaces being serial these days you do have a lot of parallel activities going on that can benefit from parallelization.

    Or take a PID loop. The input processor gathers data, and sends it off to an error calculator. Which hands it off to P, I, and D processors, which are then combined by a summing processor which delivers the result to the output processor.

    You have to think differently about problems and can’t just go with a cook book solution.

    My job, if I can do it, is to teach people how to think differently.

    We shall see. I’m getting a full up development board and will probably start out with something simple to get a feel (blinking lights and sound). And then try my hand at something more complex.

  7. Simon Avatar
    Simon

    Because this is a data flow machine the arrival of data automatically triggers the receiving processor. So data sync is not an issue.

  8. rhhardin Avatar

    Fine but then the big number isn’t a processor speed.

  9. Simon Avatar
    Simon

    Of course not. If you read the article the processor speed is 1.5 ns per instruction. The big number is computational power.

  10. rhhardin Avatar

    It’s computational power if you have a problem that matches the chip.

    Unlike a general purpose processor, which does any problem with that computational power.

    My experience is that finding matching problems is often hard.

    An array or pipeline machine bought as a general resource mostly sits idle, with perhaps a couple of programmers willing to recast problems specifically for them.

  11. Simon Avatar
    Simon

    The chip is designed for high volume applications. Like cell phones.

    Which explains the emphasis on low power.

    Hardly anyone understands Data Flow machines. I have a LOT of educating to do in order to get people up to speed.

    Note: once volume gets up the prices will blow the Parallax machines out of the water. And that is just for the large core number machines.

    They have plans for more modest sized chips that will compete very nicely at the very low end of the market. Eight and 16 pin chips. But that is a ways down the road.

    Their first test chip was a 4 core 4 pin chip – barely useful.

  12. rhhardin Avatar

    Data flow is the programming form used in specs for logic verification, if you want an existing body of work to teach from.

  13. Simon Avatar
    Simon

    rhhardin,

    I’ll look into it.

    I’m more inclined to teach by example. I have one or two in mind that should work. My first step though is just to get some LEDs to blink and maybe a bender for sound. Which is to say: get up to speed on the tools and the basics.